Research LineAccelerators |
This project aims to develop a new hardware accelerator for posit arithmetic that is compliant with the RISC-V eXtension Interface. This will allow to decouple the co-processor from the actual CPU to increase modularity and ease its reutilization in environments ranging from embedded systems to high-performance computing. The output of this project will be released as open-source hardware.
Keywords
Arithmetic, posit, IEEE-754, floating point, RISC-V, CORE-V-XIFTeam
 | Atienza Alonso David |
 | Mallasen Quintana David |
 | Schiavone Pasquale Davide |
Real numbers, as a superset of integer numbers, present unique challenges when dealing with them in a CPU. The IEEE 754 floating-point standard is the most widespread representation that tackles this problem. However, it is not the only option. In recent years, other arithmetics have been proposed both in academia and in industry. The most notable examples are Google's bfloat16, which keep the dynamic range of 32-bit floats but have fewer fraction bits, or Nvidia's Tensorfloat-32. The TF32 format, similarly to bfloat16, keeps the same 8-bit exponent as FP32 but also uses the same 10-bit mantissa as half-precision floats (FP16). These emerging formats follow the same structure as IEEE 754 floats. However, they are not the only option.
Posit arithmetic was introduced in 2017 as an alternative to represent and operate real numbers on a computer. This novel arithmetic tries to solve some of the inherent problems of floats, such as rounding and reproducibility issues, signed zero, or numerous Not a Number (NaN) representations. One of the main benefits of posit arithmetic is that they have only two special cases. The value zero and the Not-a-Real (NaR). The rest of the bit patterns are composed of four fields: sign bit, variable-length regime, 2 exponent bits, and variable-length fraction field.
Nevertheless, posits are not yet fully studied and its hardware adoption in CPUs has either been restricted to the F and D RISC-V extensions, thus excluding the quire, or limited only to the use of the quire. The quire fused operations are operations with more than two operands in which intermediate results are not rounded, but accumulated in a larger register called quire. However, recent proposals such as the open-source posit PERCIVAL RISC-V core have pushed the boundaries of general-purpose posit computation in hardware.
The eXtension interface is aimed at extending a RISC-V CPU with a coprocessor which implements an extra set of instructions. It can be used to implementstandard RISC-V extensions as for example B (bit manipulation), M (integer multiplication and division) or F/D (single/double-precision floating point). It can also be used to extend a RISC-V CPU with a custom extension.
Following this eXtension interface we can find the cv32e40x core. This is a small and efficient, 32-bit, in-order RISC-V core with a 4-stage pipeline. It is aimed at compute-intensive applications and it is compliant with the eXtension interface to add external coprocessors.
This project aims to develop a new hardware accelerator for posit arithmetic that is compliant with the RISC-V eXtension Interface. This will allow to decouple the co-processor from the actual CPU to increase modularity and ease its reutilization in environments ranging from embedded systems to high-performance computing. The output of this project will be released as open-source hardware.