Low-Power SAR A/D Converter for Biomedical Sensor Node
Master Thesis or Semester Project
Description: Our laboratory is developing an integrated, wireless biomedical signal processing platform. Its main purpose is to track and analyze the heart rhythm, i.e., ECG signals (and potentially other physiological signals) of patients, process this data to detect potential heart rhythm disorders, and transmit relevant, compressed data to a smartphone or directly to medical doctors in case of anomalies. For example, atrial fibrillation (AF) is the most common heart rhythm disorder with several millions of affected people in the USA and in Europe; integrating an ECG tracking and analysis system on a single chip and optimizing it for ultra-low power consumption for long runtimes on a single battery charge significantly enhances the chances of diagnosing and eventually treating AF.
The ECG system-on-chip consists of low-noise amplifiers (LNA), analog-to-digital converters (ADCs), an ultra-low power subthreshold microprocessor, and a radio. While LNAs and the microprocessor have already been developed, the focus of this project is on designing the ADC. Among many different ADC architectures, we choose to adopt a successive approximation register (SAR) ADC, as it is able to achieve the required resolution of 8 – 12 bits and the required sampling rate with low power consumption. The preliminary specifications for the ADC are as follows: 125 – 1kS/s, 8 – 12 bit resolution, <100fJ/conversion, 100um x 100um area in a 65nm CMOS node. We have an existing and silicon-proven reference design in a 0.35um CMOS technology, which can now be ported to our ST65nm CMOS target technology. The main challenges will be the higher process parameter variation and the lower supply voltage in the target technology.
Prerequisites: Analog / mixed-signal IC design, Cadence
Type of work: 10% study of reference design and literature review, 30% circuit design and simulation, 30% layout design, 30% post-layout simulation and verification
Supervisor: Pascal Meinerzhagen
Memory Design Space Exploration for Embedded Systems |
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Master Thesis Project
Description: Increasing application workload in modern System-on-Chips (SoCs) necessitates an efficient choice for the implementation of the storage blocks. It has been shown that given the storage parameters e.g., word-width, access pattern, total size – the performance figures of different memory implementations such as hard macros with different number of banks and standard cell-based storage implementations vary largely over a discrete design space. Unfortunately, no single tool exists to make the choice across the design space automatically, making the task of designer difficult. The goal of this thesis is to solve this important engineering issue.
Within the scope of this thesis, the student is expected to learn different memory implementation options and then create an automated design flow to select the “best” storage organization given the performance constraints and the memory access patterns of the embedded application(s). The tool flow will be integrated with a commercial processor designer and tested with state-of-the-art embedded applications.
References:
- P. A. Meinerzhagen, C. Roth and A. P. Burg. Towards generic low-power area-efficient standard cell based memory architectures. 2010 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Seattle, WA, USA, 2010.
- D. Kammler, E. M. Witte, A. Chattopadhyay, B. Bauwens, G. Ascheid, R. Leupers, H. Meyr: Automatic Generation of Memory Interfaces for ASIPs. IJERTCS 1(3): 1-23 (2010)
Prerequisites:
Sound knowledge of C++ programming, data-structure and graph-based algorithms. Good understanding of hardware description languages. Knowledge of memory architectures and processor design fundamentals is an added plus.
Supervisor: This work will be done jointly between MPSoC Architectures, RWTH Aachen and TCL, EPFL. For details: contact Prof. Dr.-Ing. Anupam Chattopadhyay ([email protected]) OR Prof. Dr. Andreas Burg ([email protected])
FPGA Implementation of a Vertcoin Miner |
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Description: Bitcoin promises distributed transactions, but large FPGA and ASIC based mining farms make the currency quite centralized. Vertcoin is a Bitcoin fork that uses the Lyra2RE mining algorithm that is (allegedly) ill-suited for hardware implementation to prevent centralization. We would like you to try to refute that claim. Hence, the project goal is to devise an FPGA implementation of the Vertcoin mining algorithm, and to compare your implementation against that for high-end GPUs. This should allow us to find out if the Vertcoin fulfil its promise.
Areas: FPGA, VHDL, cryptocurrency, blockchain
Supervisors: Alexios Balatsoukas-Stimming and Pascal Giard
Date added: 18.12.2017